#include "dma.h"


/**
 * DMA1_0  USART1_Rx NoIT
 * DMA1_1  USART1_Tx
 * DMA1_2  ADC3
 * DMA1_3
 * DMA1_4
 * DMA1_5
 * DMA1_6
 * DMA1_7  
 * 
 * DMA2_0  SPI1_Tx
 * DMA2_1  SAI3_B
 * DMA2_2
 * DMA2_3
 * DMA2_4
 * DMA2_5
 * DMA2_6  
 * DMA2_7  
 * 
 */


void MX_DMA_Init(void){

  RCC->AHB1ENR|=RCC_AHB1ENR_DMA1EN;
  RCC->AHB1ENR|=RCC_AHB1ENR_DMA2EN;

  // HAL_NVIC_SetPriority(DMA1_Stream0_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
  HAL_NVIC_SetPriority(DMA1_Stream1_IRQn,7,0);
  HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
  HAL_NVIC_SetPriority(DMA1_Stream2_IRQn,7,0);
  HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
  // HAL_NVIC_SetPriority(DMA1_Stream3_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
  // HAL_NVIC_SetPriority(DMA1_Stream4_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
  // HAL_NVIC_SetPriority(DMA1_Stream5_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
  // HAL_NVIC_SetPriority(DMA1_Stream6_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
  // HAL_NVIC_SetPriority(DMA1_Stream7_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);

  HAL_NVIC_SetPriority(DMA2_Stream0_IRQn,7,0);
  HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
  HAL_NVIC_SetPriority(DMA2_Stream1_IRQn,7,0);
  HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
  // HAL_NVIC_SetPriority(DMA2_Stream2_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
  // HAL_NVIC_SetPriority(DMA2_Stream3_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
  // HAL_NVIC_SetPriority(DMA2_Stream4_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn);
  // HAL_NVIC_SetPriority(DMA2_Stream5_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
  // HAL_NVIC_SetPriority(DMA2_Stream6_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
  // HAL_NVIC_SetPriority(DMA2_Stream7_IRQn,7,0);
  // HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);

}

void MX_DMA_DeInit(){
  
  // HAL_NVIC_DisableIRQ(DMA1_Stream0_IRQn);
  HAL_NVIC_DisableIRQ(DMA1_Stream1_IRQn);
  HAL_NVIC_DisableIRQ(DMA1_Stream2_IRQn);
  // HAL_NVIC_DisableIRQ(DMA1_Stream3_IRQn);
  // HAL_NVIC_DisableIRQ(DMA1_Stream4_IRQn);
  // HAL_NVIC_DisableIRQ(DMA1_Stream5_IRQn);
  // HAL_NVIC_DisableIRQ(DMA1_Stream6_IRQn);
  // HAL_NVIC_DisableIRQ(DMA1_Stream7_IRQn);
  
  HAL_NVIC_DisableIRQ(DMA2_Stream0_IRQn);
  HAL_NVIC_DisableIRQ(DMA2_Stream1_IRQn);
  // HAL_NVIC_DisableIRQ(DMA2_Stream2_IRQn);
  // HAL_NVIC_DisableIRQ(DMA2_Stream3_IRQn);
  // HAL_NVIC_DisableIRQ(DMA2_Stream4_IRQn);
  // HAL_NVIC_DisableIRQ(DMA2_Stream5_IRQn);
  // HAL_NVIC_DisableIRQ(DMA2_Stream6_IRQn);
  // HAL_NVIC_DisableIRQ(DMA2_Stream7_IRQn);

  RCC->AHB1ENR&=(~RCC_AHB1ENR_DMA1EN);
  RCC->AHB1ENR&=(~RCC_AHB1ENR_DMA2EN);

}



